Design for Testability and for Built-In Self Test

The course discovers the need for a new paradigm, by which designs and tests are developed in parallel, resulting in earlier time to market, higher failure detection and lower test costs. It presents simple techniques to improve observability and controllability of any circuit. Designers can readily follow such guidelines. Moreover, the course examines structured scan techniques standardized by the IEEE-1149.1 (JTAG), by other IEEE-1149.x, by the IEEE-1500, by IEEE-1687 and by the proposed IEEE-P1687.1, 1687.2 and P2653 working groups. A thorough understanding of these techniques for testability leads to similar BIST structures. The course covers memory BIST (MBIST), logic BIST (LBIST) and analog BIST. Learn built-in test (BIT) software, and its goal to provide diagnostic information as well.

The course also teaches the need at system-level to provide repair instructions through module replacement. In order to achieve the unambiguous isolation of the faulty circuits’ testability has to be assessed at the design stage – often before the circuit details are known. Explore how this can be achieved using diagnostic assessment and modeling techniques. Finally, the course evaluates the value of DFT and BIST at all levels of assembly from an economic perspective. Attendees gain a thorough understanding of the techniques and with the tools necessary to convince management that DFT and BIST will profit both manufacturing and support, while at the same time greatly improve the quality of units under test UUTs.

The course is primarily for designers and test engineers and provides great value to reliability, logistics, quality and manufacturing engineers as well. Managers concerned with testability and BIST techniques as well as those with general interest on IEEE and military standards in DFT also benefit from this course.